In today's market, demands for increased device speeds are ever-increasing and these demands are further challenging package substrate designs to enable improved chip performance. Today's telecommunications and consumer electronics continue to press towards miniaturization, low power consumption, and high integration, with higher transfer data rates. Package design in particular is more complex given the demand for high-speed devices and many of the traditional techniques are unable to provide for the needed performance. For instance, newer designs are demanding higher speeds and greater numbers of signals per application-specific integrated circuit (ASIC) package.
With the demand for high-speed differential signals, traditional approaches continue to be unable to satisfactorily provide for needed data rates, in part as these traditional approaches fail to provide for adequate isolation between the differential signals in packages, such as within a Ball Grid Array (BGA) package for example. Traditional approaches have unsuccessfully attempted to overcome these challenges by providing for vertical or horizontal offset pin assignments implementations which sacrifice density by assigning ground pins between signal pins thereby lowering the total number of signal pins. For instance, in FIG. 1, a traditional vertical pin assignment implementation (100) is set forth in which a 40 dB of isolation is realized which utilizes only 50% of pins as being assigned to signals (e.g., 110) and 50% of pins as being assigned to ground/power (e.g., 120). From FIG. 1, a differential signal pair is shown where two signal pins are connected at 130. Further, in FIG. 2, a traditional vertical pin assignment implementation (200) is set forth in which a 60 dB of isolation is realized which utilizes only 33% of pins as being assigned to signals (e.g., 210) and 67% of pins as being assigned to ground/power (e.g., 220). From FIG. 2, a differential signal pair is shown where two signal pins are connected at 230.
Therefore, traditionally, to improve the isolation, the approach often required is that additional pin spacing and/or placement of additional ground pins as between signal pins occurred to further attempt to improve isolation and reduce the effects of possible crosstalk. Unfortunately, the availability and density of active signals pins thereby decreased as a result. As a result, as will be appreciated by those skilled in the art, these traditional approaches fail to optimize the number of usable signal pins for a given amount of needed isolation in an ASIC footprint, die, or die package size. As a result, improving isolation while optimizing signal pin densities without impacting ASIC footprint size, presents challenges which traditional approaches fail to overcome.
Therefore, what is needed is an optimized approach for assigning signal pins in an optimized pattern for an ASIC arrangement to improve isolation without increasing ASIC footprint requirements.